Principal Fuse​/JTAG Design Lead

Principal Fuse/JTAG Design Lead

Arm’s Solution Engineering division develops SoCs for various application segments using the latest IP products from Arm and other vendors. We are seeking a creative and hard‑working SoC Lead Design Engineer to lead the team responsible for the development of the JTAG and Fuse Subsystems. The successful candidate will own the microarchitectural specifications, lead other designers and partner with the verification lead/team across multiple process nodes and product families.

You will join a team of dedicated engineers, collaborating with multiple other groups inside Arm to design scalable and reusable debug control and access IPs.

• Lead the IP development team for the reconfigurable Fuse and JTAG Subsystems.
• Work with architect(s) to understand subsystem requirements and develop design specifications that meet quality, reliability, manufacturing and reconfigurable needs across multiple SoC’s.
• Create design micro‑architecture specifications, develop RTL, fix bugs, run design checks and contribute to implementation constraints.
• Provide technical guidance and mentorship of the design team, and engage with partner teams for collaborative improvements in tools, technologies, methodologies and capabilities.
• Partner with the verification lead to review test plans, debug design issues and craft UVM components for IP and SoC integration of the Subsystems.
• Drive unification and efficient methods, and introduce new methodologies used by the team.
• Ensure Arm’s best solutions are adopted as "1-Arm".
• Work with Project Management to define plans and execute schedules flawlessly.

• Bachelors or Master’s Degree in Computer Science, Electrical/Computer Engineering or a similar related field and 15+ years of experience designing complex subsystems or SoCs.
• Experience in digital hardware design for complex systems using System Verilog.
• Experience with analog hard‑IP integration, timing diagrams, BMODs.
• Experience with reconfigurable IP / subsystem design.
• Experience with power and clock domain crossing.
• Experience with static design checks such as linting, CDC/RDC, X‑propagation.
• Experience with all stages of design: concept, specification, implementation, testing, documentation and support.
• Experience collaborating with the verification team on design quality closure.
• Experience with Perl, Python or other scripting languages.
• Leadership, mentoring or coaching experience.

• Experience with ARM‑based designs and/or ARM System Architectures.
• Experience developing designs for OTP/Fuse usage models and JTAG/TAP protocols.
• Experience with SoC system use cases and debug methodologies.
• Experience developing and integrating subsystems for PCIe, UCIe, DDR/LPDDR/HBM, Ethernet, etc.
• Experience with DFT use cases and methodologies: RTL testability, scan insertion, OCC.

We value a set of behaviors that reflect our culture: partner and customer focus, teamwork and communication, creativity and innovation, team and personal development, impact and influence, and delivering on promises. We also have a 10x mindset that guides how we engineer, collaborate and grow.

$241,100 – $326,100 per year.

We want to build extraordinary teams. If you need an adjustment or accommodation during the recruitment process, please email  By providing us with this information, you consent to its use by Arm to arrange an appropriate accommodation. All requests will be treated confidentially and disclosed only as necessary.

Arm’s hybrid working approach supports high performance and personal wellbeing. Teams determine their own hybrid patterns based on work and team needs. Details of the arrangement for each role will be shared during the application process.

Arm is an equal opportunity employer committed to an environment of mutual respect where equal opportunities are available to all applicants and colleagues. We do not discriminate on the basis of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or protected veteran status.