FPGA Design Engineer; Secret Clearance - Camden, NJ - JP Security Clearance

Position: FPGA Design Engineer (Secret Clearance) - Camden, NJ - JP7960 with Security Clearance
We've determined which skillsets are most beneficial for this role. These skills are listed first below as the Must Haves and Nice to Haves our hiring team highly prefers. Below that you'll find the standard job description for this opportunity. Must Haves:
* Bachelor of Science (BS) - Four year degree or from an accredited course of study in engineering, engineering technology (chemistry, physics, mathematics, data science, or Electrical/Electronics/Computer Engineering/Computer Science)
* 3-5+ years' experience designing FPGA products with VHDL
* Experience with Xilinx FPGAs and Vivado
* Experience with Revision control system
* Experience with Earned Value Management (EVM)
* Active DoD Security Clearance Nice to Haves:
* Masters (MS) or PhD from an accredited course of study in engineering, engineering technology (chemistry, physics, mathematics, data science, or Electrical/Electronics/Computer Engineering/Computer Science)
* Experience with mapping algorithms to architecture
* Experience in C++ (OOP)
* Experience with any of protocols :
Ethernet, TCP/IP, PCIe, NVMe, USB
* Experience with Xilinx SoC design with SDKs and Peta Linux OS
* Experience with High-Level Synthesis (HLS) with Vivado HLX or Mentor Catapult

Job Description:

FPGA Design Engineer
- Reporting to the Manager, Engineering (ASIC/FPGA), the Senior Member of Engineering Staff (SMES) will be part of the key design team, responsible for the delivery of FPGAs for defense applications. S/he will architect, implement FPGA design, with hands on design/debug with primarily Ethernet, I2C, SPI, AXI protocols. The company has state-of-the-art EDA flows/methodologies including Mentor EDA:
Simulator Questa Prime, Verification IP (QVIPs), UVM framework, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), Questa Lint, Synopsys (DC/Primetime/Synplify), Xilinx/Intel/Microchip EDA (Vivado/Libero/Quartus). We are a learning organization and have the capability to target all FPGA vendors and have ASIC front end capability, with mature design processes. This is a high impact role in the organization to ensure robust quality and delivery of communication products for National Security.

Essential Functions:

* Derive FPGA design specifications from system requirements
* Develop detailed FPGA architecture for implementation
* Implement design in RTL (VHDL) and perform module level simulations
* Perform Synthesis, Place and Route (PAR) and Static Timing Analysis (STA)
* Perform RTL quality using:
Lint, Reset Domain Crossing (RDC), Clock Domain Crossing (CDC), Static Formal EDA
* Generate verification test plans and perform End to End Simulations
* Support Board, FPGA bring up
* Validate design through HW/SW integration test with test equipment
* Support product collateral for NSA certification
* Good written, verbal, and presentation skills Please see our website for more job openings: