CPU Design Verification Engineer

A fantastic opportunity for an experienced Design Verification Engineer to join a global leader in semiconductors, working alongside their CPU Team in Cambridge (UK).

As a CPU Verification Engineer, Senior you will work with Chip Architects to validate the concepts of CPU and SOC level micro-architectures. You will work on a selected part of the CPU Design Verification to ensure that it functions to the standards of being launch ready for the end product.

• Working with CPU and SOC Architects to understand the concepts and high-level system requirements.
• Developing detailed Test and Coverage plans based on the Architecture and Micro-architecture.
• Developing Verification Methodology, ensuring scalability and portability across environments.
• Developing Verification environment, including all the respective components such as Stimulus, Checkers, Assertions, Trackers, and Coverage.
• Developing Verification Plans and Test benches for your functional domain.
• Executing Verification Plans, including Design Bring-up, DV environment Bring-up, Regressions enabling all features under your care, and Debug of the test failures.
• Tracking and report DV progress using a variety of metrics, including Bugs and Coverage.

• Deep knowledge of Micro-Processor Verification functions and Architectures, in domains such as:
  Cache Coherence, Memory ordering and Consistency, Prefetching, Branch Prediction, Renaming, Speculative execution, and Address Translation/Memory Management.
• Knowledge of Random Instruction Sequencing (RIS) and testing a given design, at the Block/Unit-level and Subsystem/Chip-level for proving correctness.
• Experience in leading a small team of Verification engineers performing CPU Verification.
• Advance techniques such as:
  Formal, Assertions, and Silicon bring up, is helpful.
• In-depth knowledge of Micro-processor functions, Architectures, and Micro-architectures.
• Experience in writing Test plans, portable Test benches, Transactors, and Assembly code.
• Experience with different Verification Methodologies and Tools such as Simulators, Coverage collection, Gate-level Simulation, Waveform viewers, and Formal Proof Tools.
• Ability to develop and work independently on a Block/Unit of the design.

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