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AI Chip Toolchain Architect

Job in California City, Kern County, California, 93504, USA
Listing for: Forestown
Full Time position
Listed on 2026-01-12
Job specializations:
  • Software Development
    AI Engineer, Software Engineer
Salary/Wage Range or Industry Benchmark: 60000 - 80000 USD Yearly USD 60000.00 80000.00 YEAR
Job Description & How to Apply Below
About the job AI Chip Toolchain Architect

Job Responsibilities

1. Be responsible for the overall architecture design and planning of Horizon's AI toolchain. Design a system architecture and overall solution that meet the requirements, and track and support the implementation of requirements during the product R & D process. Conduct feasibility assessments of key core technologies of the project and assist in improving the product definition.

2. Focus on the long-term technical competitiveness of the AI toolchain. Think from the perspectives of model deployment and model compression

3. Be responsible for the R & D of the model quantization and compression tool. Conduct mid - and long - term planning for AI model deployment, model compression, and model quantization technologies to ensure the technical competitiveness of the AI chip toolchain in the fields of model quantization and model compression.

4. Undertake the system and architecture design of the model quantization tool. Analyze and decompose the system problems during the deployment of AI models for autonomous driving.

Job Requirements

1. A master's degree or above in computer science or a related major. More than 5 years of work experience in model deployment and model compression, or more than 10 years of experience in AI algorithm development, architecture design, or technical management. Have an in - depth understanding of the latest AI technologies and trends.

2. Be familiar with the end - to - end details of AI model deployment, including but not limited to model quantization, compilation, and edge - side deployment optimization. Have a deep understanding of key technologies such as model compression (especially post - quantization), model deployment, etc., and be able to conduct mid - and long - term technical planning proficiently.

Have an accurate prediction of the development of the model deployment field and have a relatively in - depth understanding and recognition of at least one mainstream deployment optimization tool, such as Tensor

RT.

3. Understand the business problems and pain points in the development process of algorithms for intelligent driving and human - machine interaction, as well as the development models. Be able to transform domain technologies and models (such as model conversion and optimization technologies, compiler technologies) into engineering architectures. Have an in - depth understanding of the future evolution of algorithms and application development models for autonomous driving and human - machine interaction, and have an in - depth understanding of the development models for algorithms and applications.

4. Be able to evaluate multiple alternative solutions, make architecture decisions, determine priorities, and guide the project and the organization in the right direction. Have strong abstraction ability to simplify complex problems and transform high - level architecture technical planning into detailed design.

5. Have strong programming skills. Be proficient in the development, upgrading, and maintenance of complex C++ system projects and have in - depth thinking at the system architecture level.

6. Have strong communication and collaboration abilities and documentation skills. Collaborate with other architects and stakeholders, align goals, document the architecture design and decisions, and communicate them to the team to unify cognition. Be able to clearly express and convey your design to the team and guide developers to implement it correctly. Preferably with experience in complex software system development.

7. Preferably with experience in AI compilers, PTQ/QAT, GPT large models, algorithms for autonomous driving and human - machine interaction, and AI architecture development.

8. Preferably with published papers on model compression and deployment in core conference journals or experience in the development of mainstream AI chip tool chains.

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