Edge AI SOC System Architect

Position: Staff Edge AI SOC System Architect
About Analog Devices
Analog Devices, Inc. (NASDAQ: ADI ) is a global semiconductor leader that bridges the physical and digital worlds to enable breakthroughs at the Intelligent Edge. ADI combines analog, digital, and software technologies into solutions that help drive advancements in digitized factories, mobility, and digital healthcare, combat climate change, and reliably connect humans and the world. With revenue of more than $9 billion in FY24 and approximately 24,000 people globally, ADI ensures today's innovators stay Ahead of What's Possible™.

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Role Summary
We are building a pioneering organization dedicated to advancing the next generation of Edge AI heterogeneous compute SOCs.
We are seeking a Staff Edge AI SOC System Architect to lead our architecture exploration and design of an ultra-efficient edge-compute SOC.
As an SOC System Architect, you will explore multiple architectural approaches that could deliver potential breakthroughs in power efficiency, latency, and area. You will collaborate with internal and external teams on analog and digital NN compute IPs, define processor cores, peripherals, signal processing accelerators, and interfaces into digital sub-systems. You’ll define the architecture of future ASICs to power drones supporting intelligent tasks.

You will work with product domain experts, embedded AI, AI, and compute core designers to ensure the SOC architecture meets needs and pushes efficiency to the edge
Key Responsibilities :

• Translate SoC product requirements into a complete system architecture, including well-defined specifications for IP blocks, firmware, processors, and AI compute subsystems.

• Conduct competitive benchmarking of drone flight controllers and mission-computer SoC architectures, analyzing performance, power, cost, and feature differentiation.

• Develop architectural prototypes using Synopsys Platform Architect or alternative simulation tools to demonstrate potential PPAL (performance, power, area, latency) outcomes for proposed designs.

• Build performance and behavioral models for digital and analog neural-network compute systems, utilizing tools such as MATLAB, C/C++, System

C, and Python.

• Integrate multi-processor configurations and heterogeneous NN compute paradigms into system-level models, enabling comprehensive architectural exploration and concept validation within Platform Architect.

• Define hardware block specifications and, when required, contribute to modeling or RTL design of components using Verilo
Minimum Qualifications :

• Master’s degree in computer engineering, Electrical Engineering, or a related technical field.

• 7+ years of experience with digital and analog SoC systems, including hands-on work with digital signal processing and both analog and digital neural-network compute architectures.

• Strong expertise in System

C modeling and virtual prototyping, with demonstrated capability in building and analyzing complex system-level models.

• Deep understanding of processor architecture and design, including digital processing data paths, bus and memory architectures, processor peripherals, chip-level interfaces, security subsystems, analog-in-memory compute (AIMC) neural network blocks, and digital NPUs.

• Proven ASIC design experience, encompassing high-speed and low-power RTL development as well as familiarity with physical design flows and constraints.

• Proficiency with advanced verification methodologies, including UVM, System Verilog, System

C, random test generation, functional coverage, and assertion-based verification

• Excellent verbal and written communication skills, with the ability to clearly articulate technical concepts to diverse audiences.

• Strong programming skills in C, along with experience in additional programming languages commonly used in modeling, simulation, or design.

• Demonstrated intelligence, drive, enthusiasm, and a strong work ethic-valued as highly as specific technical expertise
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