Senior IP Design Engineer; FPGA​/Adaptive SoC

Position: Senior IP Design Engineer (FPGA / Adaptive SoC)
Location

UK/Belfast/ any Eastern European Countries, United Kingdom# Senior IP Design Engineer (FPGA / Adaptive SoC) at N Consulting Ltd Location

UK/Belfast/ any Eastern European Countries, United Kingdom Salary €200 - €250 /dayJob Type Contract Date  Posted March 4th, 2026

Apply Now Senior IP Design Engineer (FPGA / Adaptive SoC)

Location:

100% Remote (UK, Belfast, or Eastern Europe)  Type: 6 months Contract Overview  We are seeking a highly skilled Senior IP Design Engineer to design and develop high-performance IP cores targeting FPGA and Adaptive SoC technologies. This is a fully remote opportunity open to candidates based in the UK (including Belfast) and Eastern Europe.  The ideal candidate will have deep expertise in System Verilog RTL design and a strong understanding of FPGA design flows, including place & route and timing closure.

Key Responsibilities  Design and implement high-performance, synthesis-ready IP cores using System Verilog RTL  Develop IP for high-speed interfaces such as 100

Gb Ethernet, PCIe Gen5, and AMBA/AXI  Drive FPGA/Adaptive SoC design flow including synthesis, place & route (P&R), and timing closure  Optimize designs for performance, area, and power  Work closely with verification, system, and software teams for seamless IP integration  Develop automation scripts using Python and Tcl  Maintain high-quality code using Git and support CI/CD workflows  Support integration, bring-up, and debugging activities as required

Required Skills & Experience  Strong experience in System Verilog RTL design  Proven expertise with:  100

Gb Ethernet  PCIe Gen5  AMBA/AXI protocols  Deep understanding of FPGA/Adaptive SoC architecture and design flows  Hands-on experience with synthesis, place & route, and timing closure  Strong working knowledge of Vivado/Vitis  Proficiency in Python and Tcl scripting  

Experience with Git and CI/CD environments  Ability to work independently in a remote, distributed team

Preferred Qualifications  

Experience with high-speed data path design  Familiarity with performance optimization techniques for large FPGA designs  Exposure to lab bring-up and hardware debugging  Experience mentoring junior engineers
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