Senior ASIC Designer: RTL, Verification & Synthesis

A technology company in Beaverton, OR, is looking for a Senior ASIC Design Engineer to architect and design ASIC blocks. The candidate will be responsible for writing microarchitecture specifications, collaborating with team members, and utilizing Verilog for design and System Verilog for verification. A BA/MS degree and over 5 years of experience in ASIC design are required. Ideal candidates will have experience with digital design practices, FPGA emulation, and knowledge of USB or PCIe standards.
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