Senior ASIC Design Engineer

Overview

Senior ASIC Design Engineer — Server Logic
• Beaverton, OR, United States

• Architect a block of an ASIC and write a microarchitecture specification (MAS) for the block
• Collaborate with other team members to integrate the block with the full chip
• Use Verilog to design and System Verilog for block level verification
• Assist the Verification team in reviewing and debugging test cases
• Run LINT and CDC checks on the RTL code and fix accordingly
• Assist with synthesis and FPGA emulation

• BA/MS degree and 5+ years of relevant work experience
• Demonstrate knowledge of Verilog for chip design and verification
• Must understand the ASIC flow from MAS to silicon including RTL design, verification, synthesis, timing constraints, GLS, FPGA prototyping, and first silicon bring up and debug
• Understanding of digital design and verification practices
• Be able to take a specification, write RTL and simulation vectors to verify their RTL
• One prior RTL design is a requirement
• Experience with USB 2.0, USB 3.2, USB4, or PCIe is desired