Circuit and Library Characterization: Standard Cell and SRAM

Location: Bengaluru

Circuit and Library Characterization:
Standard Cell and SRAM

Experience:

10+ Years
Strong expertise in  characterization and modeling of standard cell libraries and SRAM macros  across multiple PVT corners, ensuring accurate timing, power, and noise modeling for advanced technology nodes.
Deep understanding of  SRAM architectures  including single-port, dual-port, two-port, pseudo dual-port, and multiport register file implementations, with the ability to interpret transistor-level designs and ensure accurate characterization coverage.
Experience in  characterizing SRAM sub-systems and peripheral circuits , including control logic, I/O latches, clock gating, row decoders, read/write assist circuits, sense amplifiers, clocking networks, tracking circuits, precharge/discharge paths, reset logic, and internal timing margins.
Proficient in  SRAM macro characterization and validation , including modeling of:
Read/write timing arcs
Bit/byte write functionality
Assist and margin control circuits
Address programmability
Redundancy and repair mechanisms
DFT features and test modes
Power gating behavior
Strong experience in  standard cell library characterization , including sequential and combinational cells such as latches, flip-flops, clock gating cells, adders, multipliers, and custom arithmetic blocks.
Hands-on expertise in generating and validating  complete timing, power, and noise models , including:
NLDM/CCS timing and power models
LVF (Liberty Variation Format) for statistical timing analysis
Internal power and leakage characterization
State-dependent and multi-mode arcs
EM/IR aware power modeling where applicable
Proven experience performing  comprehensive Liberty QA and sign-off checks , including timing consistency, arc completeness, waveform integrity, and correlation with SPICE simulations.
Strong ability to  debug characterization issues , improve model accuracy, and ensure correlation between  SPICE simulations, characterization outputs, and STA results .
Experience developing and maintaining  automated characterization flows and regression frameworks  for large libraries and complex memory macros.

EDA Tools and Flows
Hands-on experience with industry-standard characterization and simulation tools including:
Circuit Simulation & Extraction
Cadence Virtuoso
StarRC, Quantus
HSPICE, Prime Sim XA, Spectre, Prime Sim CCK
Variation, Modeling & Analysis
Solido HSV
Spectre FMC
Nano Time
Library Characterization
Liberate
Liberate MX
Silicon Smart
Experience in  large-scale characterization automation, regression management, and library QA flows  for standard cell and memory IP delivery.