Principal GPU and Diagnostic Software Architect

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AMD is seeking a Sr level Engineer to lead company‑level innovation in GPU microarchitecture performance measurement, parallel programming optimization, and advanced software diagnostics. This role centers on deep technical leadership in performance attribution, hardware/software observability, and defect localization across GPU compute stacks. In this role you will define and architect next‑generation methodologies for microarchitectural analysis, counter design, instrumentation, and diagnostic tooling that enable precise performance understanding from silicon through runtime and application layers.

This individual will work closely with GPU architecture, silicon design, firmware, drivers, compiler/runtime, and tools teams to ensure AMD platforms deliver measurable, explainable, and reproducible performance across generations.

Are you a hands‑on architect in areas like GPU/accelerator or HPC performance engineering, microarchitecture analysis, compilers, runtime systems, and diagnostics?

• Define AMD’s methodology for cycle‑accurate and counter‑driven performance attribution across GPU generations.
• Architect performance measurement frameworks that correlate workload behavior to microarchitectural structures (CUs/SIMDs, wavefront schedulers, issue pipelines, register files, memory hierarchy, cache systems, fabric/interconnect).
• Drive counter architecture definition and validation to ensure observability of pipeline stalls, cache contention, memory divergence, synchronization overhead, and scheduling inefficiencies.
• Establish rigorous approaches for bottleneck classification: compute‑bound, memory‑bound, latency‑bound, fabric‑bound, and occupancy‑limited regimes.
• Develop scalable performance modeling techniques linking pre‑silicon simulation, emulation, and post‑silicon telemetry.

• Architect end‑to‑end performance workflows: microbenchmarks, workload decomposition, instrumentation, trace capture, and guided optimization.
• Lead development of profiling and visualization systems exposing pipeline stages, wave occupancy, cache behavior, memory bandwidth utilization, atomic/synchronization costs, and interconnect utilization.
• Influence compiler and runtime optimizations including code generation, scheduling, register allocation, vectorization, tiling, kernel fusion, and launch configuration strategies.
• Drive auto‑tuning and kernel optimization frameworks for AI/HPC workloads (GEMM, convolution, attention, graph workloads) across GPU generations and heterogeneous system configurations.
• Ensure strong correlation between synthetic benchmarks, application kernels, and real‑world workloads.

• Architect diagnostic frameworks capable of detecting, isolating, and reproducing defects across silicon, firmware, driver, runtime, and application layers.
• Develop static and dynamic analysis tools tailored to GPU execution and memory consistency models.
• Lead development of GPU‑focused sanitizers, race detectors, memory checkers, hang analysis tools, and fuzzing frameworks.
• Build automated triage systems integrating telemetry, crash signatures, counter anomalies, and workload traces to accelerate root cause identification.
• Drive methodologies for deterministic repro, workload minimization, and differential testing across hardware stepping and driver/compiler…