Machine Learning Engineer; AI​/ML

Are you a builder at the frontier of Edge AI/ML, eager to apply your craft to high-impact, real-world problems? Do you thrive in ambiguous spaces where data, silicon, and algorithms intersect? Cirrus Venture Labs (CVL) may be the place for you.

CVL is Cirrus Logic’s newly formed technology accelerator, chartered to develop disruptive, scalable, and monetizable innovations that solve endemic industry problems. Our vision is to be a globally recognized innovation engine that repeatedly shapes and transforms semiconductor markets. We do so by embedding intelligence directly where signals originate in the physical world, across Voice, Sense, and Control domains, and pioneering ML-augmented signal processing.

As a Principal ML Engineer, you will be a hands‑on technical leader shaping CVL’s machine learning programs. You will drive the development of ML models, frameworks, and prototyping pipelines, spanning data generation, curation, model engineering, and optimization for deployment on Edge and mixed‑signal systems. Partnering closely with Innovation Managers, Architects, external ventures, and away‑team contributors, you will turn ambitious hypotheses into validated prototypes that can be scaled into new product categories for Cirrus Logic.

• Prototype Development: Lead rapid prototyping of ML models for edge intelligence across Voice, Sense, and Control domains, tightly integrated with Cirrus Logic’s mixed‑signal processing strengths.
• Data & Model Engineering: Build datasets, design model architectures, and optimize performance, efficiency, and interpretability. Explore advanced approaches in ML‑augmented signal processing, anomaly detection, and adaptive control.
• System Integration: Collaborate with silicon, firmware, and systems teams to co‑design ML architectures that operate efficiently on constrained hardware and embedded systems, balancing algorithmic accuracy with compute and power budgets.
• Exploration & Research: Stay at the forefront of ML frameworks, foundation/SLM trends, and physical‑world AI applications. Scout external IP, academic work, and startups to inform CVL’s ML strategy.
• Mentorship & Technical Leadership: Provide guidance and technical direction to away‑team engineers and contributors across Cirrus Logic. Share best practices in ML model lifecycle, from experimentation to deployment.
• Cross‑Functional
  
  Collaboration:
  
  Work hand‑in‑hand with Innovation Managers, advisory teams, customers, and external partners to identify opportunities, define success criteria, and validate ML‑enabled innovations in real‑world scenarios.
• Impact Assessment: Help define benchmarks, evaluation metrics, and pass/fail criteria that ensure ML prototypes address significant industry problems with clear paths to monetization.

• Educational Background: Master’s or Ph.D. in Computer Science, Electrical Engineering, or related field with a focus on ML/AI.
• Experience: 8+ years of hands‑on experience developing and deploying ML systems on the Edge and within embedded platforms, including ownership of datasets, model development, and deployment pipelines. Proven experience implementing ML inference on resource‑constrained systems such as microcontrollers, embedded SoCs, or custom silicon.
• Architectural Expertise: Demonstrated experience with CNNs, RNNs (LSTM/GRU), and Transformer‑based models, including custom architecture design and optimization for production. Experience tailoring these architectures for low‑latency and low‑power embedded inference.
• Technical Depth: Strong understanding of representation learning, attention mechanisms, sequence‑to‑sequence modeling, and generative architectures. Ability to translate these methods into efficient implementations suited for real‑time sensor, audio, or control workloads.
• Optimization for Edge: Experience with quantization, pruning, knowledge distillation, mixed‑precision training, and compiler‑level optimizations to deploy models on CPUs, DSPs, NPUs, or hybrid SoC architectures. Familiarity with memory hierarchy tradeoffs, compute‑offload, and bandwidth constraints in embedded ML.
• Embedded & Firmware Integration: Proficiency…