Principal Static Timing Analysis Engineer
Job in
Austin, Travis County, Texas, 78716, USA
Listed on 2026-03-01
Listing for:
Silicon Labs
Full Time
position Listed on 2026-03-01
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Hardware Engineer, Electrical Engineering
Job Description & How to Apply Below
**** Austin, TX
** This position involves the development of timing constraints and timing closure signoff of low power Wireless SoCs and IP systems. These SoC devices are multi-core, multi-threaded processor subsystems with multi-level cache, capable of supporting multiple wireless protocols and application functionality, such as sensor hub, AI /ML and are specified to exceed best-in-class power targets. These SoCs deploy a complex, deeply gated clock network with many asynchronous clock sources.
** Responsibilities
* ** Develop timing constraints at both the IP and SoC level in collaboration with the designers
* Improve or evolve existing static timing analysis flows and methodologies.
* Develop required timing signoff criteria, such as aging, on chip variation, and signal integrity
* Analyze timing reports using scripting techniques to develop insights and drive rapid timing closure
* Collaborate with a global design team to resolve complex static timing issues
* Collaborate with a multi-functional team to drive timing closure for mixed-signal IP integration
** Skills You Will Need
*** Minimum Qualifications
** 15+ years in Industry
* Bachelor or Master’s degree in Electrical or Computer Engineering
* In depth knowledge of the timing closure flow and methodology
* Experience in timing constraint development, both functional and test modes (such as scan)
* Hands-on experience with static timing tools, such as Tempus or Primetime
* In depth knowledge of scripting languages like Perl, Python, Tcl, shell
* Knowledge of timing closure modes and corners
* Knowledge of low power design methodology (static/dynamic clock gating, power gating, dynamic voltage and frequency scaling)
* Knowledge of timing model generation of mixed signal IP
* Knowledge of design flows including Lint, CDC, Synthesis, Logic Equivalence, DFT, Place and Route
* Knowledge of Verilog and System Verilog
* Experience with artificial intelligence (AI) powered tools and technologies used to enhance productivity, analysis, and decision-making
** Benefits & Perks*
* * You can look forward to the following benefits:
* 401k plan with match and Roth plan option
Additional benefit options (Commuter benefits, Legal benefits, Pet insurance)
At Silicon Labs, we hire and empower great talent to achieve their full potential. By offering challenging projects, technical mentorship, and continuous learning opportunities, we ensure our employees thrive at every stage of their careers. Here, you’ll work alongside some of the industry’s brightest minds, tackling complex problems that deepen your expertise and expand your horizons. Whether you’re building new skills or shaping your career path, we’re dedicated to supporting your growth and celebrating your success every step of the way.
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