SoC Physical Design Engineer, PnR

We are seeking a seasoned Physical Design technical leader with deep expertise in high-performance & low-power design. In this highly visible role, you will work closely with cross-functional teams to come up with efficient chip and IP physical architecture taking into account physical design constraints early in the design cycle.

- You will be responsible for all aspects of physical design implementation from RTL2

GDS including PnR, bump/RDL, STA, physical verification, EMIR, sign-off.

- You will also collaborate to drive methodologies and "best-known methods" to streamline PD work and develop guidelines and checklists.

- You will be the primary technical contact for your focus area and are motivated to solve more challenging timing closure issues, area & power optimization etc.

• Minimum BS and 3+ years of relevant industry experience

• Knowledgeable in partition level P&R implementation including floor planning, clock & power distribution, timing closure, and physical & electrical verification.
• Knowledge of PD construction & analysis flows and methodology.
• Strong interpersonal skills.
• Recent successful tapeouts in deep submicron technology.
• Experience with large SOC designs (>20M gates) with frequencies in excess of 1
  
  GHZ.
• Shown ability to execute to stringent schedule & die size requirements.
• Experienced in industry standard tools and understanding their capabilities and underlying algorithms.

Apple is an equal opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant .

Apple accepts applications to this posting on an ongoing basis.