Front End Design Engineer

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APPLE INC has the following available in Austin, Texas. Design synthesis to convert functional Register Transfer Level code to digital logic gates in physical chip design. Conduct formal equivalence to ensure the generation of a functional design of the chip. Perform Static timing analysis and constraint development to ensure that the physical design meets timing requirements. Perform power integrity checks to ensure that the various power domains and their interfaces are complete.

Signoff checks to develop and maintain flows that help verify the overall quality of the chip designs. Engineer Change Order implementations to meet the overall functionality and timing closure of the design. Work with the CAD team and tool vendors to identify and resolve any flow or integration issues. Create innovative flows and processes to support new chip designs. Lint checks, to ensure the overall quality of Register Transfer Level code meets the guidelines.

Optimize logic designs to achieve low power, low area, high performance and timing goals. Generate GDSII file with synthesis, floor-planning, routing, verification, ECO, and timing analysis. 40 hours/week.

• Master’s degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field.
• Education and/or experience must include:
• Experience designing compiler/Genus to generate synthesis netlist.
• Experience in TCL scripting to query or mine data or automate flow
• Power Analysis and techniques to design power saving for the devices
• Using Primetime for timing analysis
• RTL for understanding the design and making edits
• Logic equivalent check to ensure the synthesis netlist generated matches the design intent
• Using Innovus and Calibre to implement Physical design, and experience in verification and generating GDSII

• N/A

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Apple accepts applications to this posting on an ongoing basis.