Global CPU Design Lead, Silicon

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in silicon design with a focus on IP (CPU, GPU, or TPU).
• Experience leading technical teams and RTL design projects to tape-out.
• Experience with SoC infrastructure design (e.g., clocking, reset sequences, power intent/UPF).

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with ARM architecture and AMBA protocols (AXI, ACE, CHI).
• Experience as a unit lead or design manager for processor projects.
• Understanding of CPU subsystem integration, debug architectures (Core Sight), or secure boot flows.
• Ability to lead distributed teams and execute effectively in a cross-functional environment.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Global Design Lead, you will join the CPU Silicon Engineering team to architect and deliver the foundational infrastructure that enables our high-performance processors to function. You will own the "global" logic subsystems within the CPU, encompassing clock generation, reset domains, power management integration, and debug/trace fabrics. In this role, you will lead the technical definition and execution of these critical blocks, ensuring they meet rigorous performance requirements and integrate seamlessly into the top-level System-on-Chip (SoC).

You will lead a distributed engineering team through the full design life-cycle, from micro-architecture and RTL implementation to logic synthesis and post-silicon bring-up, while collaborating closely with cross-functional partners to resolve integration issues.

• Lead the micro-architecture, design, and delivery of CPU subsystem infrastructure, including Clocks, Resets, Boot, and Debug/Trace logic.
• Drive the integration of the CPU into the top-level SoC, managing standard interfaces (e.g., AXI, APB, CHI) and cross-functional dependencies.
• Manage the execution of the design life-cycle from concept to tape-out, overseeing logic synthesis, static checks (Lint/CDC), and engineering deliverables.
• Collaborate with verification, physical design, and post-silicon validation teams to ensure functionality and successful bring-up.
• Mentor and manage a technical team, fostering growth and collaboration across multiple global sites.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law.

See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

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