Lead Emulation Engineer

Overview

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5-10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first-party data to drive the next major computing revolution.

We are seeking an experienced Emulation Lead to drive pre-silicon hardware verification and validation using emulation and prototyping platforms. This role is critical to ensuring silicon success by enabling early software development, system-level validation, and accelerated functional verification of complex SoC/ASIC designs. The Emulation Lead will own the emulation strategy end-to-end and work cross-functionally with design, verification, software, and physical design teams.

This is a unique opportunity to be a part of a newly formed HW engineering org and have an influence on our products and processes as we move from the initial stages of product development to market release and scaled volume production. Join our team and help us shape the future of computing at the edge and beyond!

• Define and own the overall emulation strategy, including platform selection (e.g., Cadence Palladium, Synopsys ZeBu, Siemens Veloce), capacity planning, and scheduling across multiple projects.
• Establish methodologies, flows, and best practices for emulation bring-up, debug, and regression.
• Evaluate and adopt new emulation/prototyping technologies (e.g., FPGA prototyping) as needed.
• Lead the synthesis, partitioning, mapping, and compilation of RTL designs onto emulation platforms.
• Resolve design issues that impede emulation readiness, including unsynthesizable constructs, clock/reset architecture issues, and memory modeling challenges.
• Develop and maintain emulation-specific design wrappers, clock generators, and reset sequencing logic.
• Enable and support full-chip and system-level validation scenarios, including processor boot, firmware execution, OS bring-up, and peripheral/IO exercising.
• Collaborate with software and firmware teams to provide early pre-silicon environments for driver development, BSP validation, and performance benchmarking.
• Build and maintain reference test environments that replicate real-world system configurations.
• Work with the verification team to port and accelerate simulation-based test benches onto the emulation platform, leveraging speed-up for long-running or system-level tests.
• Define hybrid emulation/simulation (transaction-based) methodologies to interface verification IP and bus functional models with emulated DUT.
• Support coverage-driven verification closure through emulation-based regression runs.
• Develop robust debug methodologies including signal visibility planning, waveform extraction, hardware-assisted probing, and assertion-based debug on emulation.
• Build and maintain scripts, automation, and CI/CD integration for emulation compile, run, and regression flows.
• Manage emulation lab infrastructure, including hardware resources, licensing, networking, and access control.
• Partner with RTL design teams on design-for-emulation guidelines, including clock domain management, memory replacement strategies, and design partitioning.
• Coordinate with physical design and DFT teams to ensure emulation models stay aligned with the latest design state.
• Work with silicon validation teams to ensure continuity from pre-silicon emulation to post-silicon bring-up.

• Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 10+ years of experience in ASIC/SoC design or verification, with at least 5 years of hands‑on emulation experience.
• Emulation Platforms: Deep expertise with one or more major platforms — Cadence Palladium/Protium, Synopsys ZeBu/HAPS, or Siemens Veloce.
• RTL & Design
  
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