Engineering Director - Verification IP

Siemens EDA is a global technology leader in Electronic Design Automation software. Our tools enable companies worldwide to develop highly innovative electronic products faster and more cost‑effectively.

• Role is based in Austin and involves working with teams that impact entire cities, countries, and the shape of future products.
• Work with field engineers (PEs) and account engineers (AEs) or directly with customers to deploy and resolve customer issues.
• Participate in development of comprehensive verification IPs for interfaces such as PCIe Gen5/Gen6, USB
  3.2, 400 GbE, DDR5, LPDDR5 and coherency protocols like CXL for use with Questa RTL simulation.

• B.Tech/M.Tech in Electronics or a related field from a reputed institute.
• 15+ years of working experience in RTL design, IP/VIP development, verification or emulation with industry leadership.
• Strong knowledge of System Verilog and UVM; experience with assertions, coverage, test plans, BFMs, debugging, loggers and trackers.
• Understanding of register layering and bus protocols such as PCIe, CXL, USB, Ethernet, Memory, CHI, etc.
• Experience with C/System
  
  C based tests is an added advantage.
• Knowledge of coherent and non‑coherent NOC, understanding of various components (CPU, GPU, display, network, device, memory).
• Familiarity with system‑level performance metrics such as latency, bandwidth and overall performance.

We do not discriminate on the basis of race, religion, color, national origin, sex, gender, gender expression, sexual orientation, age, marital status, veteran status or disability status. We are an equal‑opportunity employer and value diversity at our company.

We offer a comprehensive rewards package, including a competitive base salary, bonus scheme, generous holiday allowance, pension, and private healthcare.