Power Architect

Efficient is developing the world’s most energy-efficient general-purpose computer processor. Efficient’s patented technology uses 100x less energy than state of the art commercially available ultra-low-power processors and is programmable using standard high-level programming languages and AI/ML frameworks. This level of efficiency makes perpetual, pervasive intelligence possible: run AI/ML continuously on a AA battery for 5‑10 years. Our platform’s unprecedented level of efficiency enables IoT devices to intelligently capture and curate first‑party data to drive the next major computing revolution

We are seeking a uniquely skilled Power Architect who can own the full lifecycle of chip power — from early architectural power strategy and modeling through to physical implementation, verification, and silicon sign‑off. This role bridges the gap between power architecture decisions made at the system and microarchitecture level and their physical realization in RTL, synthesis, place‑and‑route, and signoff. It is ideal for someone who understands that power decisions made at the architecture stage have cascading consequences in implementation, and who can drive coherent, optimized outcomes across both domains.

This is a senior technical leadership role with high visibility, requiring deep expertise in low‑power design techniques, power‑aware physical implementation, and the ability to influence architectural trade‑offs and implementation execution simultaneously. This is a unique opportunity to get in at the early stages of a hardware engineering organization and have influence on our products as we move from initial stages of product development to market release and scaled volume production on multiple product lines.

Join our team and help us shape the future of computing at the edge and beyond!

• Help define the chip‑level power architecture — voltage domains, power islands, power modes, state machines, and transition sequencing aligned with product use cases and thermal budgets
• Own the DVFS strategy — defining voltage‑frequency operating points, regulator requirements, and software/firmware interfaces for dynamic power management
• Work across teams to author and primarily own the UPF specification as the golden power intent document across the full design cycle from architecture through implementation sign‑off
• Drive early accurate power modeling and estimation at the architectural level to guide design decisions before RTL is available. Partner with RTL/PD teams to get more accurate data for power model building blocks.
• Guide RTL designers/PD on power‑efficient design practices — clock gating strategies, operand isolation, memory shutdown/retention, and activity reduction techniques
• Drive power‑aware design flows — ensuring correct insertion of isolation cells, level shifters, retention registers, power switches, and multi‑Vt optimization. Vector driven PD build flows and RTL flows to assess and improve power. You dont improve what you dont measure.
• Design the power delivery network (PDN) — defining grid topology, metal layer assignment, strap widths, via density, and decoupling strategy for each voltage domain to ensure consistent grid design across the chip ensuring we dont have to jack up power post‑si to meet performance goals and jeopardize our power goals.
• Drive IR drop and electromigration analysis and signoff using tools like Red Hawk, Voltus across all power modes and workload scenarios
• Define power switch placement and sizing strategy — balancing rush current, wake‑up time, voltage droop, and area overhead
• Own chip‑level power analysis and budgeting from early RTL estimation through gate‑level vectored analysis to final signoff, tracking against targets throughout the design cycle
• Lead power reduction campaigns — identifying dominant contributors and deploying targeted techniques such as Vt swapping, clock gating improvements, and voltage optimization
• Own the power‑aware verification strategy — ensuring all power state transitions, isolation, retention, level shifting, and sequencing are thoroughly verified via UPF‑driven simulation
• Collaborate with package and thermal teams o…