Lead Mixed Signal Design Verification Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. The Lead Mixed‑Signal Verification Engineer is responsible for defining mixed‑signal verification plans, models, and roadmaps and delivering complete mixed‑signal DV solutions that address challenges across the full spectrum of diverse mixed‑signal products. The role also includes driving innovation across the mixed‑signal verification flow to create efficient and accurate methodologies.

The ideal candidate is expected to be a mixed‑signal DV expert and the hub between all engineering teams.

• Architect, develop, champion, and implement metric‑driven mixed‑signal verification solutions in the areas of digital/DMS/AMS testbench creation and generation
  • Automatic model generation and testing
  • Cadence Design Systems AMS simulation flows
  • Mixed‑signal assertions and checkers
  • Behavioural modelling and model validation methodologies
  • Mixed‑signal VIP integration and testing
  • Mixed‑signal emulation flows and practices
• Power intent verification including low‑power states, state retention, and CPF/UPF integration
• Push technology for mixed‑signal modelling, simulation, and DV to improve verification efficiency and accuracy
• Ensure scalable mixed‑signal DV solutions to cover the breadth of IPG offerings including Ser Des, DDR, A2D converters, and custom solutions
• Drive adoption of analog behavioural modelling methodologies for efficient mixed‑signal verification
• Develop efficient debug solutions and techniques
• Develop an efficient and accurate full‑stack mixed‑signal methodology for the entire IP stack from the controller to the analog circuit
• Propagate mixed‑signal knowledge and mentor junior engineers
• Collaborate closely with:
• Digital, Analog, Firmware, and Test engineers
• Internal methodology and tool development teams such as Virtuoso/ADE/Xcelium and PDK teams
• Customer management and engineering support teams

• 4+ years’ experience in working with digital and analog mixed‑signal environments and teams
• Excellent written and verbal cross‑functional communication skills
• Proven experience in the following areas:
  • Creating verification infrastructure (test‑bench, environment, scripting)
  • Scripting of verification flows and design automation
  • Debugging verification test cases
  • Knowledge of existing and upcoming standards such as PCIe, USB, DDR4, etc.
• Comfortable interacting across the IPG development team and understanding design constraints
• Knowledge of multiple programming languages (C++, Python, System Verilog, e – verification language) is a plus
• Knowledge of mixed‑signal Cadence tools and mixed‑signal methodology is a plus
• Knowledge of System Verilog and UVM test environment and methods is a plus
• Working knowledge of revision control tools such as SVN or equivalent is a plus
• Bachelor’s Degree (MSEE/PhD preferred)

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