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Verification Team-Leader Engineering

Job in Austin, Travis County, Texas, 78716, USA
Listing for: Retym Israel Ltd
Full Time position
Listed on 2026-02-28
Job specializations:
  • Engineering
    Systems Engineer, Software Engineer, Electronics Engineer, Test Engineer
Salary/Wage Range or Industry Benchmark: 100000 - 125000 USD Yearly USD 100000.00 125000.00 YEAR
Job Description & How to Apply Below
Position: Verification Team-Leader Engineering · Full-time

For an exciting well-funded start-up, developing leading edge technology of the next generation high speed communication, we are looking for a Verification Team-Leader to be driving into the complicated RTL design verification activity on various design aspects.

Requirements

Key Responsibilities

  • Lead, mentor, and manage a team of verification engineers to meet project milestones and deliverables.
  • Define and execute verification strategies and plans for complex digital blocks and systems.
  • Oversee the development of robust and reusable verification environments using System Verilog and UVM.
  • Review and approve verification plans, test benches, and coverage metrics.
  • Drive functional and coverage-based verification across multiple block/system verification cycles.
  • Collaborate with design engineers to debug and resolve functionality issues.
  • Ensure effective resource allocation and project planning to achieve optimal results.
  • Foster a culture of technical excellence, continuous learning, and innovation within the team.
  • Report verification progress, issues, and risks to senior management and other stakeholders.

Required Qualifications

  • 10+ years of experience in digital design verification—a must
    .
  • 3+ years of experience managing or leading verification teams
    .
  • Proven track record of completing two or more full block/system verification cycles
    .
  • In-depth knowledge of VLSI verification flows
    , concepts,
    methodologies and interfaces with algorithmic models and SW.
  • Expertise in verification using System Verilog
    , UVM
    , or other industry-standard methodologies (eRM, OVM).
  • Experience in block, cluster and full chip verification levels.
  • Strong problem-solving skills and the ability to debug complex functionality issues.
  • Excellent leadership, communication, and organizational skills to manage and inspire a team.

Preferred Qualifications

  • Hands-on experience with high-speed communication protocols like Ethernet
    , PCIe, or Ser Des.
  • Proficiency in scripting languages (e.g., Python, Perl) for automation of verification processes.
  • Familiarity with formal verification techniques and tools.
  • Background in system-level verification or post-silicon validation.
  • Experience with project planning tools and methodologies for effective team management.
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