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ASIC Engineer, Design

Job in Austin, Travis County, Texas, 78716, USA
Listing for: Meta
Full Time position
Listed on 2026-02-28
Job specializations:
  • Engineering
    Systems Engineer, Hardware Engineer, Software Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 146000 - 209000 USD Yearly USD 146000.00 209000.00 YEAR
Job Description & How to Apply Below

Summary

Meta is seeking highly skilled Design Engineers to join our team. In this role, you will contribute to the development of advanced technology solutions, including machine learning, graphics, display, and network acceleration. You will collaborate with world‑class researchers and engineers to design, implement, and optimize low‑power hardware accelerators, state‑of‑the‑art SoCs, and custom silicon solutions that enable the next generation of innovative devices and hardware.

Required

Skills

ASIC Engineer, Design Responsibilities:

  • Develop micro‑architecture, RTL coding, and design verification for complex IPs
  • Work with architects to map algorithms onto the hardware and specify requirements for IP and subsystems integration
  • Assist performance/power analysis of the design and help meet power and performance targets
  • Collaborate with adjacent teams such as Verification, Physical Design, and Design‑for‑Test
  • Drive IP/sub‑system micro‑architecture and RTL design in collaboration with DV and PD leads
  • Minimum Qualifications
  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 6+ years of experience as a Hardware Design Engineer for production silicon shipped in volume
  • Experience in digital design Microarchitecture, RTL coding, SoC integration and micro‑architecture development
  • Demonstrated communication and collaboration skills
  • Preferred Qualifications
  • Master’s or PhD degree in Electrical Engineering, Computer Science or related areas
  • Experience in CPU, NOC, Memory, Die‑to‑die and Peripheral Subsystems
  • Experience with Synthesis, Timing Closure and Formal Verification Methodology
  • Experienced in managing SOC‑level boot flow, Silicon Debug architectures and PLL/sequencing clocks and resets within SOC architectures
  • Public Compensation

    $146,000/year to $209,000/year + bonus + equity + benefits

    Industry

    Internet

    Equal Opportunity

    Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics.

    We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E‑Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.

    Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at

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