DFT Engineer 1st priority

For an exciting, well-funded start-up, we are looking for a DFT Engineer
.

As a DFT Engineer
, you will work closely with all other design teams – backend, VLSI, verification, and analog. You will be fully responsible for defining, implementing, and deploying advanced design-for-test (DFT) methodologies for highly complex digital and mixed-signal chips. Your work will involve silicon test strategies, DFT/DFD, BIST for next-generation SoCs.

• 5+ years of experience in DFT specification definition, architecture, insertion, and analysis in designs
• Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG-related issues
• Experience in fault modeling

Preferred qualifications:

• Master's degree in Electrical Engineering
• Experience in IP integration (memories, Test controllers, TAP, MBIST)
• Experience using EDA Test tools like Design/Fusion Compiler, DFT Max, Spy Glass, Modus, Tessent, and Test Kompress
• Experience and understanding of ASIC DFT, synthesis, simulation, and verification flow
• Excellent attention to detail, organizational, problem-solving, and communication skills

Responsibilities:

• Implement SoC DFT strategy and architecture (ATPG/DFT/MBIST)
• Work on hierarchical design
• Debug all Design Rule checks and apply design fixes to achieve high test quality
• Insert all DFT logic-boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks
• Insert and connect MBIST logic
• Work on test plan for special analog IPs and implement