Design Test Engineer

Overview

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible.

We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

The role is Staff Design for Test (DFT) for high-performance designs going into industry leading AI/ML architectures. The person coming into this role will be involved in all implementation aspects from RTL to tapeout for various IPs on the chip. High level challenges include reducing test cost while attaining high coverage, and facilitating debug and yield learnings while minimizing design intrusions.

The work is done collaboratively with a group of highly experienced engineers across various domains of the ASIC.

This role is hybrid, based out of Santa Clara, CA or Austin, TX

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

• Implementation of DFT features into RTL using verilog.
• Understanding of DFT Architectures and micro-architectures.
• ATPG and test coverage analysis using industry standard tools.
• JTAG, Scan Compression, and ASST implementation.
• Gate level simulation using Synopsys VCS and Verdi.
• Support silicon bring-up and debug.
• MBIST planning, implementation, and verification.
• Support Test Engineering on planning, patterns, and debug.
• Develop efficient DFx flows and methodology compatible with front end and physical design flows

• BS/MS/PhD in EE/ECE/CE/CS with at least 5 years of industry experience in advanced DFx techniques.
• DFx experience implementing in finFET technologies.
• Experience with industry standard ATPG and DFx insertion CAD tools.
• Familiarity with System Verilog and UVM.
• Fluent in RTL coding for DFx logic including lock-up latches, clockgates, and scan anchors.
• Understanding of low-power design flows such as power gating, multi-Vt and voltage scaling.
• Good understanding of high-performance, low-power design fundamentals.
• Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, and Cell Aware.
• Exposure to post-silicon testing and tester pattern debug are major assets.
• Experience with Fault Campaigns a plus.
• Strong problem solving and debug skills across various levels of design hierarchies.

Compensation and Benefits: Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.

To apply, please follow the official career posting and submit your application through the designated portal.