Digital Test Engineer – Chip Design

Summary

Well‑funded hardware startup (with $180 MM in recent funding, backed by leading VCs) seeks an experienced DFT Engineer to innovate and own design‑for‑test (DFT) methodologies for advanced digital and mixed‑signal SoCs. This hands‑on role collaborates cross‑functionally to define, implement, and deploy robust DFT strategies for next‑generation programmable DSP chips powering the world’s fastest AI and cloud infrastructure.

• 5+ years in DFT specification, architecture, insertion, and analysis for complex silicon.
• Experience with silicon bring‑up, debug/validation of DFT on ATE, ATPG, MBIST, and JTAG.
• Proficiency in ASIC DFT, synthesis, simulation, and verification.
• Strong organizational and problem‑solving skills; detail oriented.
• Willingness to work on‑site in Austin, TX (relocation not covered).
• Preferred:
  Master’s degree in Electrical Engineering.
• Preferred: IP integration experience with memories, test controllers, MBIST, and TAP.
• Preferred:
  Expertise in EDA tools such as DFT Max, Tessent, Modus, Design/Fusion Compiler, Spy Glass, and Test Kompress.

• Lead and implement SoC DFT architecture and ATPG/MBIST strategy.
• Insert, validate, and debug all DFT logic – scan chains, BIST, boundary scan, TAP, compression, and MBIST.
• Own silicon bring‑up and ATE debug for new test features and DFT IP.
• Collaborate to improve test coverage, resolve RTL violations, and streamline test processes.
• Develop and maintain formal DFT documentation.

Austin, Texas – On‑site, 5 days/week.

Base salary: $170,000 – $200,000 USD per year + equity (4‑year vesting).

Visa: H1‑B sponsorship available.