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Systems Engineer

Verification Engineer - SystemVerilog​/UVM Expert

Job in Austin, Travis County, Texas, 78716, USA
Listing for: Mirafra Technology
Full Time position
Listed on 2026-01-19
Job specializations:
  • Engineering
    Systems Engineer
Salary/Wage Range or Industry Benchmark: 80000 - 100000 USD Yearly USD 80000.00 100000.00 YEAR
Job Description & How to Apply Below
A software service organization is looking for professionals skilled in System Verilog and test bench creation to enhance their verification processes. Candidates should have experience with UVM, VMM, and OVM methodologies, along with knowledge of CPU Memory Subsystem and ARM architecture.

This role offers opportunities for professional growth within an evolving industry environment in Austin, Texas.
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