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Lead DV Engineer: CPU Verification & UVM Expert

Job in Austin, Travis County, Texas, 78716, USA
Listing for: Cadence Design Systems
Full Time position
Listed on 2026-01-15
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Test Engineer, Engineering Design & Technologists
Job Description & How to Apply Below
A leading electronic design automation company in Austin seeks a Design Verification Lead Engineer to manage verification projects. The role involves developing verification plans, debugging complex RTL failures, and ensuring comprehensive test coverage. Ideal candidates should have a

B.S/M.S in Electrical and Electronic Engineering, 5-8+ years of experience in VLSI design verification, and proficiency in System Verilog Assertions and scripting. This position offers full-time opportunities with a collaborative team environment.
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