Design Verification Engineer Austin, TX

DESCRIPTION

Project Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low‑latency, high‑speed broadband connectivity to unserved and underserved communities around the world.

The Role:

• Implement a state of the art verification environment to facilitate testing of the RTL against reference Matlab/C models
• Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program
• Participate in the validation of ASIC implementations in Verilog/System Verilog
• Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM
• Develop a highly automated environment to run regressions that can be used to make builds and maintain organization of the database

Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum.

• Bachelor's degree in Electrical / Communications Engineering or Computer Science, or related field, or equivalent experience
• 2+ years in verification preferably in communication systems
• 2+ years in UVM