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SoC Design Verification Engineer; SystemVerilog​/UVM

Job in Austin, Travis County, Texas, 78716, USA
Listing for: Altera
Full Time position
Listed on 2026-01-13
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Hardware Engineer, Engineering Design & Technologists
Salary/Wage Range or Industry Benchmark: 128900 - 205900 USD Yearly USD 128900.00 205900.00 YEAR
Job Description & How to Apply Below
Position: SoC Design Verification Engineer (SystemVerilog/UVM)
A leading technology firm is seeking a SoC Design Verification Engineer in Austin, Texas. In this role, you will perform functional verification of integrated SoCs and develop scalable verification plans. Applicants should have over 7 years of experience in logical hardware design and be proficient in System Verilog. This is a full-time position offering a competitive salary ranging from $128.9K to $205.9K, reflecting the skills and experience required for the role.
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