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Digital Design Engineer at Meta – Sunnyvale, CA | Redmond, WA | Austin, TX

Job in Austin, Travis County, Texas, 78716, USA
Listing for: Victrays
Full Time position
Listed on 2026-01-12
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer, Software Engineer, Hardware Engineer
Salary/Wage Range or Industry Benchmark: 142000 - 203000 USD Yearly USD 142000.00 203000.00 YEAR
Job Description & How to Apply Below

Digital Design Engineer – Meta – Sunnyvale, CA | Redmond, WA | Austin, TX

As a Digital Design Engineer at Meta Reality Labs, you will work with a world‑class group of researchers and engineers, and use your digital design skills to implement and contribute to the development and optimization of state‑of‑the‑art vision and sensing algorithms. You will also support the Digital Silicon Architects in developing and implementing the next generation custom and semi‑custom mixed‑signal ICs to drive our industry‑leading virtual and augmented reality systems.

Digital

Design Engineer Responsibilities
  • Responsible for top‑level or block‑level µArchitecture definition and design of Computer Vision/Image Sensing IP.
  • Contribute to chip‑level integration, verification plan development and verification.
  • Define timing constraints, run synthesis and static timing analysis.
  • Support the test program development, chip validation and chip life until production maturity.
  • Work with FPGA/Emulation engineers to perform early prototyping.
  • Support hand‑off and integration of blocks into larger SOC environments.
  • Assist with performance/power analysis of the design and help meet the power requirements.
Minimum Qualifications
  • 7+ years of experience as a Digital Design Engineer.
  • Experience with top level integration using automation tools.
  • Experience in RTL coding, synthesis and/or SoC integration.
  • Experience in digital design Microrchitecture.
  • Experience with at least 1 procedural programming language (C, C++, Python, etc.).
  • Bachelor’s degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.
Preferred Qualifications
  • Experience with Computer Vision or Image Signal Processing accelerators.
  • Experience with HLS flow for data path implementation.
  • System Verilog OVM/UVM experience.
  • Experience in SoC integration and ASIC architecture.
  • Experience with low power design and optimization, including UPF flow.
  • Experience with design synthesis and timing optimization.
  • Master’s degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience.

For those who live in or expect to work from California if hired for this position, please  for additional information.

US $142,000/year to US $203,000/year + bonus + equity + benefits

Individual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.

Equal Employment Opportunity. Meta is proud to be an Equal Employment Opportunity employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, reproductive health decisions, or related medical conditions), sexual orientation, gender identity, gender expression, age, status as a protected veteran, status as an individual with a disability, genetic information, political views or activity, or other applicable legally protected characteristics.

You may view our Equal Employment Opportunity notice here .
Meta is committed to providing reasonable accommodations for qualified individuals with disabilities and disabled veterans in our job application procedures. If you need assistance or an accommodation due to a disability, fill out the Accommodations request form.

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