Senior Design Verification Engineer

Responsibilities

Perform pre-silicon verification for complex IP, including creating test plans, developing Universal Verification Methodology (UVM) components and environments from scratch, writing test cases, debugging failures to root cause issues, running and maintaining regression suites, and closing coverage. Interact with architects and design engineers to create test plans covering verification strategy, test requirements, and test environments for IP/SS/SOC level verification. Define verification strategy, requirements, and test environments for IP/SS/SOC level verification.

Create test-plans and write tests to provide complete features coverage. Develop and implement technical solutions to complex quality and design challenges. Develop verification components like scoreboards, sequences, constraints, assertions and functional coverage. Triage and debug testbench, simulation, and emulation failures. Develop Makefiles and scripts for verification infrastructure. Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment. Collaborate with teams across sites and geographies.

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Master’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 4+ years technical engineering experience OR Bachelor’s Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 5+ years technical engineering experience OR equivalent experience. In depth knowledge of verification principles, test benches, stimulus generation, and UVM based test environments.

Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments. Experience with verification for product from definition to Silicon, including writing test plans, developing tests, debugging failures and coverage signoff in C/C++ and Universal Verification Methodology (UVM). Scripting language such as Python or Perl or shell scripts. 10+ years of design verification experience with Universal Verification Methodology (UVM), System Verilog and Verification Fundamentals.

Verification experience for an IP or SS or SOC related to CPUs, VPUs, GPUs, Tensor unit, or similar. Knowledge of System Verilog class, constraints, coverage and assertions. Experience in scripting languages such as Python or Perl. Hands‑on experience in Formal property verification, formal verification of computational data path designs.

This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information.

To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.

Microsoft