Staff Engineer, Coherent Interconnect Design Verification

Staff Engineer, Coherent Interconnect Design Verification

Join to apply for the Staff Engineer, Coherent Interconnect Design Verification role at Samsung Semiconductor
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Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high‑performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world.

Come build with us!

• You ensure design excellence and thorough verification by contributing to key features, driving test planning, verifying design feature accuracy, and performing coverage analysis to identify improvement opportunities.
• You develop reusable verification environments and test benches, including stimulus, assertions, checkers, cover groups, and System Verilog constraints.
• You debug and root cause functional failures from regressions, and help with silicon debug.
• You perform coverage gap analysis, identifying coverage exclusions and improving stimulus.
• You are a key player in test plan and code reviews.
• You contribute to power‑aware verification with UPF and gate‑level simulations.
• You collaborate with design, SoC, physical design, and performance verification teams to debug failures, resolve spec issues, and enable successful bring‑up across IP, SoC, and silicon.
• You exemplify an ownership culture and inspire an inclusive, high‑performing culture by mentoring junior engineers, fostering trust, and making data‑driven decisions through open communication.

• 6+ years of experience with a Bachelor’s degree in Computer Science/Computer Engineering or relevant technical field; or 4+ years with a Master’s degree; or 2+ years with a PhD.
• Must have experience with interconnect.
• Proficiency in ARM protocols – CHI/AXI/ACElite, APB.
• Expert hands‑on coding skills in System Verilog and UVM.
• Experience with Git version control, Unix/Perl scripting.
• Excellent communication and collaboration skills, with the ability to navigate ambiguity in a fast‑paced, global team environment.

The System IP & SoC Architecture team at SARC/ACL designs proprietary coherent interconnects and memory controllers that power Exynos SoCs for Samsung’s premium consumer devices. We play a critical role in shaping the technology roadmap, delivering scalable, performance‑ and power‑optimized IP solutions that support advanced system modeling and real‑world applications such as gaming and computational photography. With scalability and efficiency at the core of our designs, our IP integrates seamlessly into complex semiconductor products, enabling cutting‑edge memory subsystem capabilities across diverse market segments.

Joining our team means collaborating alongside talented engineers from diverse technical backgrounds across a global organization. You’ll have the opportunity to build next‑generation technologies, broaden your expertise, and solve impactful challenges in a supportive environment built on collaboration, continuous learning, and growth.

At Samsung – SARC/ACL, base pay is one part of our total compensation package and is determined within a range. The base pay range for this role is between $151,000 and $226,600. Your actual base pay will depend on variables that may include your education, skills, qualifications, experience, and work location.

Samsung employees have access to benefits including medical, dental, vision, life insurance, 401(k), onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and many more. In addition, regular full‑time employees (salaried or hourly) are eligible for MBO bonus compensation, based on company, division, and individual performance.

Additionally, this role might be eligible to participate in a long‑term incentive plan and relocation.

This is an exempt position, which is not eligible…