Lead CPU Architect

Position Summary

Samsung, a world leader in advanced semiconductor technology, is founded on a simple philosophy – the endless pursuit of excellence will create a better world for all. At Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL), we are building a center of excellence for Intellectual Property (IP) that is applied to high-performance computing devices (mobile, automotive, and other custom market segments) consumed by millions of people around the world.

Come build with us!

We are seeking an exceptionally skilled and seasoned Lead CPU Architect to join our team at Samsung SARC/ACL. As a technical leader, you will not only lead a high-performing team, but also actively contribute to the design and development of cutting‑edge CPU architectures for Samsung's Exynos flagship SoCs. Your expertise will be instrumental in shaping architectural strategy, driving rigorous quantitative performance analysis, and ensuring the seamless integration of advanced CPU features within intricate SoC environments.

• You lead a team of talented engineers to design and develop next‑generation CPU architectures that meet Samsung's PPA requirements.
• You drive forward‑looking CPU roadmap strategy and influence CPU microarchitecture and implementation flows.
• You ensure architectural excellence by defining and implementing new CPU features, including vector processing, AI accelerators, security extensions, and memory safety features.
• You conduct in‑depth quantitative analysis of key mobile benchmarks and correlate hardware PMU stats to optimize CPU performance.
• You develop and maintain CPU architecture simulation tools (gem5, QUME) to evaluate design trade‑offs.
• You collaborate with cross‑functional design teams to seamlessly integrate CPU architectures into SoC designs and maximize system‑level PPA.
• You inspire high performance by mentoring engineers, promoting open communication and data‑driven decision making, encouraging innovative thinking and calculated risk taking.
• You stay current with industry trends and advancements in CPU architecture, machine learning, and AI accelerators.

• 20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years of experience with a Master’s Degree, or 16+ years of experience with a Ph.D.
• Deep expertise with Armv8/v9 (or x86 and RISCV) ISA and extensions, particularly in the areas of vector/AI/security/memory safety features (such as Realms, memory tag extension) and their use cases
• Strong fundamentals in key computer architecture concepts such as virtualization, interrupts, pipelining (e.g., CPI, branch prediction, prefetching), cache hierarchies, cache and MP coherency, and memory subsystems
• Proven ability to perform quantitative analysis of key mobile benchmarks such as Geekbench6/7 and SPECCPU
  17, and correlation/interpretation of hardware PMU stats (e.g., cache misses, TLB misses, etc.)
• Hands‑on experience using and developing CPU architecture simulation tools such as gem5 or QUME.
• Excellent programming skills in C, C++, and/or Python.
• Excellent analytical and problem‑solving skills, with the ability to identify bottlenecks, propose solutions and guide teams through execution.
• Strong written/verbal communication and collaboration skills, with the ability to work effectively in a cross‑functional team environment.

• Experience with CPU microarchitecture and implementation flows.
• Ability to read and analyze RTL code efficiently (Verilog or System Verilog).
• Familiarity with CPU micro‑architecture and implementation techniques that maximize PPA.
• Knowledge of system‑on‑chip (SoC) design and integration.
• Experience with machine learning and AI accelerators.
• Contributions to open‑source projects or CPU architecture communities.

The System IP & SoC Architecture team at SARC/ACL designs proprietary coherent interconnects and memory controllers that power Exynos SoCs for Samsung’s premium consumer devices. We play a critical role in shaping the technology roadmap, delivering scalable, performance‑ and power‑optimized IP solutions that…