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Prototyping and Emulation Engineer

Job in Austin, Travis County, Texas, 78716, USA
Listing for: Info Way Solutions
Full Time position
Listed on 2026-01-12
Job specializations:
  • Engineering
    Systems Engineer, Hardware Engineer, Software Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 80000 - 100000 USD Yearly USD 80000.00 100000.00 YEAR
Job Description & How to Apply Below

Job Title:

Prototyping and Emulation Engineer

Location:

Markham, ON & Austin, TX Client: AMD

We are seeking a highly skilled and motivated FPGA Prototyping and Emulation Engineer to join our hardware development team. This role is critical to accelerating silicon validation and system-level debug through advanced prototyping and emulation platforms. You will work closely with architecture, design, and verification teams to enable early software development and system bring‑up.

The Person :

We’re on the lookout for an Engineer with strong experience in semiconductor validation and hardware/software co‑debug. Ideal candidates will have worked on advanced SoC designs and validation methodologies, with prior experience developing large‑scale SoC models (1B+ gates) and applying expert debug techniques.

Key Responsibilities:
  • Develop and maintain FPGA‑based prototypes using Xilinx FPGAs and Synopsys HAPS platforms.
  • Perform FPGA synthesis, partitioning, and timing closure for complex SoC designs.
  • Drive bring‑up and debug of SoC prototypes, including waveform capture and analysis.
  • Interface with custom PCBs and semiconductor components for system‑level validation.
  • Collaborate with cross‑functional teams to support pre‑silicon and post‑silicon debug.
  • Integrate and support emulation platforms including Synopsys ZeBu, Cadence Palladium/Protium, and Mentor Veloce.
  • Use AI‑based modeling to generate behavioral models of removed modules.
  • Maintain and monitor quality model development, deployment, and automated regression testing infrastructure.
  • Develop and maintain model "smoke tests" to ensure model functionality prior to delivery to bring‑up teams.
  • Drive technical innovation across validation, including tool and script development, methodology enhancement, and cross‑functional initiatives.
  • Debug issues across bring‑up, validation, and production phases of SoC programs.
  • Track test execution and ensure timely validation and optimization of all features.
  • Engage with other software/hardware modeling frameworks and support teams.
  • Lead collaborative efforts across multiple engineering teams.
Required Qualifications:
  • Strong hands‑on experience with Xilinx FPGA architecture and tool chains.
  • Expertise in Verilog/System Verilog design and simulation.
  • Proficiency with FPGA synthesis and partitioning tools (e.g., Synplify, Vivado).
  • Experience with Synopsys HAPS prototyping platforms.
  • Solid understanding of SoC bring‑up, debug methodologies, and waveform analysis.
  • Familiarity with PCB bring‑up and hardware/software interfacing.
  • Proficiency with C/C++, low‑level boot code, and firmware development.
Preferred Qualifications:
  • Experience with emulation platforms such as Synopsys ZeBu, Cadence Palladium/Protium, or Mentor Veloce.
  • Understanding of BIOS for system, x86, and ARM cores.
  • Knowledge of scripting languages (Python, Tcl, Perl, Ruby) for automation and tool integration.
  • Background in semiconductor validation and hardware/software co‑debug.
  • Prior development of large SoC models (1B gates+).
  • Strong debug techniques and methodologies.
  • Extensive experience with lab equipment (protocol/logic analyzers, oscilloscopes, etc.).
  • Deep experience with board/platform‑level debug, delivery, sequencing, and optimization.
  • Strong knowledge of system architecture and validation strategy.
  • Excellent analytical and problem‑solving skills with attention to detail.
  • Self‑starter with the ability to independently drive tasks to completion.
Academic Credentials:

Bachelor’s or Master’s degree in Electrical Engineering or Computer Engineering

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