ASIC Engineer Verification
Job in
Austin, Travis County, Texas, 78716, USA
Listing for:
Meta
Full Time
position
Listed on 2026-01-12
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 173000 - 249000 USD Yearly
USD
173000.00
249000.00
YEAR
Job Description & How to Apply Below
Position: ASIC Engineer, Performance & Package Verification
Summary
Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for data center applications. As a Design Verification Engineer, you will be part of an agile team working with the best in the industry, focused on developing innovative ASIC solutions for Facebook’s data center applications.
You will be responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure. Along with traditional simulation, you will use other approaches like Formal and Emulation to achieve a bug‑free design. The role also provides ample opportunities to partner and collaborate with full stack software, hardware, ASIC Design, Emulation and Post‑Silicon teams towards creating a first‑pass silicon success.
Required
Skills
Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verificationDevelop functional tests based on verification test planDrive Design Verification to closure based on defined verification metrics on test plan, functional and code coverageDebug, root‑cause and resolve functional failures in the design, partnering with the Design teamCollaborate with cross‑functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design qualityDevelop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industryMinimum Qualifications
Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experienceTrack record of 'first-pass success' in ASIC development cycles8+ years of hands‑on experience in System Verilog/UVM methodology and/or C/C++ based verification8+ years experience in IP/sub-system and/or SoC level verification based on System Verilog UVM/OVM based methodologiesExperience in one or more of the following areas along with functional verification: SV Assertions, Formal, EmulationExperience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environmentsExperience in architecting and implementing Design Verification infrastructure and executing the full verification cyclePreferred Qualifications
2+ years of experience in performance verification for CPU, GPU, or AI accelerator architecturesHands‑on experience with architecture‑level performance test planning, execution, and closureExperience with compute and/or memory subsystem and/or collective performance verificationFamiliarity with host and system‑level concepts for performance verificationExperience with chiplet‑based architectures and package‑level integration verificationExposure to industry‑standard performance benchmarks and workload characterizationPrior experience with full‑chip or package‑level integration projectsPublic Compensation
$173,000/year to $249,000/year + bonus + equity + benefits
Industry
Internet
Equal Opportunity
Meta is proud to be an Equal Employment Opportunity and Aff… (full EEO statement omitted for brevity)
Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.
Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at
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