×
Register Here to Apply for Jobs or Post Jobs. X

Arithmetic Formal Verification Engineer

Job in Austin, Travis County, Texas, 78716, USA
Listing for: Intel Corporation
Full Time position
Listed on 2026-01-12
Job specializations:
  • Engineering
    Systems Engineer, Electronics Engineer
Salary/Wage Range or Industry Benchmark: 80000 - 100000 USD Yearly USD 80000.00 100000.00 YEAR
Job Description & How to Apply Below
#
** Welcome!**## .Arithmetic Formal Verification Engineer page is loaded## Arithmetic Formal Verification Engineer locations:
US, Oregon, Hillsboro:
US, California, Folsom:
US, California, Santa Clara:
US, Texas, Austin time type:
Full time posted on:
Posted Todayjob requisition :
JR0278623#
** Job Details:**##

Job Description:

The world is transforming - and so is Intel. Intel is a company of bold and curious inventors and problem solvers who create some of the most astounding technology advancements and experiences in the world. With a legacy of relentless innovation and a commitment to bring smart, connected devices to every person on Earth, our diverse and brilliant teams are continually searching for tomorrow's technology and revel in the challenge that changing the world for the better brings.

We work every single day to design and manufacture silicon products that empower people's digital lives. Come join us and do something wonderful.

We are looking for a highly skilled Arithmetic Formal Verification Engineer to join our silicon design team. This role focuses on the formal verification of complex arithmetic hardware blocks, including fixed-point and floating-point datapaths. You will play a critical role in ensuring the mathematical correctness and corner-case robustness of arithmetic-intensive designs used in next-generation compute architectures.

*
* Key Responsibilities:

** Develop and execute formal verification strategies specifically targeting arithmetic logic units (ALUs), floating-point units (FPUs), dividers, multipliers, and custom math blocks.  Develop formal verification test benches and properties for arithmetic hardware designs.  Collaborate with RTL designers to understand microarchitectural details and identify verification targets.  Write and debug formal arithmetic specifications.  Use formal tools (e.g., Jasper Gold, VC Formal, One Spin) to prove correctness or find corner-case bugs.  

Analyze counterexamples and work with design teams to resolve issues.  Contribute to the development of verification methodologies and best practices.  Document verification plans, results, and coverage metrics.##
*
* Qualifications:

***
* Minimum Qualifications:

*** You must possess a B.S. in Computer Engineering/ Electrical Engineering or any STEM Degree with 6+ years of experience listed below;
* OR a M.S. in Computer Engineering/ Electrical Engineering or any STEM Degree with 4+ years of experience listed below;
* OR a PhD in Computer Engineering/ Electrical Engineering or any STEM Degree with 6+ months of experience listed below.
** The experience must include the following areas:
*** Strong understanding of digital design fundamentals, especially arithmetic circuits (e.g., adders, multipliers, dividers, floating-point units).
* Hands on experience with industry standard formal verification tools such as Jasper Gold, Questa Formal, VC Formal.
* Experience with formal abstractions and other complexity reduction techniques.
* Experience with a hardware modeling language, such as Verilog, VHDL, or System Verilog and industry standard logic simulation tools.
* Experience in assertion writing, checker development, coverage analysis, failure debug, root cause analysis.
*
* Preferred Qualifications:

*** Knowledge of arithmetic computational formats.
* Knowledge of theorem proving, model checking, or SAT/SMT solvers.
* Knowledge of Intel Architecture ISA and system architecture, x86 assembly language.
* Experience working in large-scale SoC or IP development environments.
* Computer architecture knowledge with emphasis on out of order processor execution, memory hierarchy, and memory management.
* Post-silicon debug and analysis.## Job Type:Experienced Hire##

Shift: Shift 1 (United States of America)## Primary

Location:

US, Oregon, Hillsboro## Additional Locations:

US, California, Folsom, US, California, Santa Clara, US, Texas, Austin## Business group:

The Silicon Engineering Group (SIG) is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs from architecture to manufacturing readiness that power Intel’s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.## Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.## ## Position of Trust

N/A
** Benefits:
** We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health,…
To View & Apply for jobs on this site that accept applications from your location or country, tap the button below to make a Search.
(If this job is in fact in your jurisdiction, then you may be using a Proxy or VPN to access this site, and to progress further, you should change your connectivity to another mobile device or PC).
 
 
 
Search for further Jobs Here:
(Try combinations for better Results! Or enter less keywords for broader Results)
Location
Increase/decrease your Search Radius (miles)

Job Posting Language
Employment Category
Education (minimum level)
Filters
Education Level
Experience Level (years)
Posted in last:
Salary