Senior MXS Verification engineer

Senior Mixed Signal Verification Engineer

Austin, TX

For an exciting well‑funded start‑up developing next‑generation high‑speed communication technology, we are looking for a Sr Mixed‑Signal Verification Engineer.

• Develop verification strategies for digital and analog (mixed‑signal) designs, utilizing UVM methodologies based on specifications.
• Create behavioural models for analog blocks in accordance with guidelines provided by analog designers.
• Write, execute, and debug test benches using UVM methodology and System Verilog code for mixed‑signal blocks.
• Run and debug behavioural model (BM) validation using AMS tools to ensure correctness of the behavioural models.
• Perform and troubleshoot unit‑level, cluster‑level, and top‑level simulations of mixed‑signal designs.

• 10+ years of experience
• Experience in behavioural modeling (BM) of analog design for digital verification
• Knowledge of mixed‑signal dynamic verification using chip digital design tools (no AMS)
• Experience in Verilog/System Verilog coding
• Experience in Virtuoso schematics tools
• Basic knowledge in analog design

• Experience in UVM
• Experience with both Synopsys and Cadence tools is an advantage

• Familiarity with verification methodologies and tools, including simulators, waveform viewers, execution automation, and coverage collection. Proven experience in developing scalable and portable test cases.
• Ability to verify analog/mixed‑signal designs in a collaborative team environment.
• Strong communication skills, including the ability to write test plans, present results, and communicate clearly with multidisciplinary teams.