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Verification Engineer
Job in
Austin, Travis County, Texas, 78716, USA
Listed on 2026-01-12
Listing for:
Retym, Inc
Full Time
position Listed on 2026-01-12
Job specializations:
-
Engineering
Systems Engineer, Electronics Engineer, Engineering Design & Technologists, Software Engineer
Job Description & How to Apply Below
Join to apply for the Verification Engineer role at Retym, Inc
For an exciting well‑funded start‑up, developing leading‑edge technology of the next generation high‑speed communication, we are looking for a Senior Verification Engineer to drive the complicated RTL design verification activity on various design aspects.
Requirements
- 5+ years of experience – a must
- Performed at least 2 or more full block/system verification cycles.
- In depth knowledge in VLSI verification flow, languages and concepts.
- Experience in data path or data protocols, specifically Ethernet – preferred
- Verification using one of the known methodologies (eRM, UVM).
Responsibilities
- Plan and perform verification of digital design blocks according to the design specification and interacting with design engineers.
- Build verification environments using System Verilog and UVM.
- Identify and write all types of coverage measures for corner‑cases.
- Debug the functionality with design engineers.
- Perform coverage collection and follow the metrics to close the full functionality.
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