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ASIC Design Verification Engineer

Job in Andover, Essex County, Massachusetts, 05544, USA
Listing for: Broadcom Inc.
Full Time position
Listed on 2026-02-23
Job specializations:
  • Engineering
    Software Engineer, Systems Engineer
Salary/Wage Range or Industry Benchmark: 108000 - 172800 USD Yearly USD 108000.00 172800.00 YEAR
Job Description & How to Apply Below
ASIC Design Verification Engineer page is loaded## ASIC Design Verification Engineer locations:
USA-CA Irvine Alton Parkway Bldg 2:
USA-MA-Andover-Brickstone Square-Suite 101:
USA-CO Broomfield time type:
Full time posted on:
Posted Todayjob requisition :
R025121
*
* Please Note:

**** 1. If you are a first time user, please create your candidate login account before you apply for a job. (Click Sign In > Create Account)
**** 2. If you already have a Candidate Account, please Sign-In before you apply.**##
*
* Job Description:

*** Would you like to become part of a stable team
* *** developing silicon products for Ethernet systems in the Cloud
****** accelerate AI/ML workflows****!  This team
* *** develops high throughput Ethernet solutions**
* * that deliver unprecedented performance at critically important power efficiency.
** We are looking for highly skilled and efficient
* *** Constrained Random Design Verification engineers**
* * that want to verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using
* *** System Verilog and UVM****.  You can become a member of an extremely skilled and efficient group of engineers.
** This is a rare opportunity to be part of a team that leads products for a
* *** new line of devices****. The candidate will work with our worldwide design and architecture teams to develop leading edge products.
* *** All aspects of Design Verification will be involved, along with opportunities for technical leadership.
***
* Skills:

Self motivated personality with a strong presence to do things right. Need to have a strong sense of teamwork and ability to work well with other.
* *** Constrained random verification methodologies with experience driving completion via coverage closure****.
**** Preferable to have skills with SV and UVM, well versed in OOP
**** Tools/

Languages:

* *** System Verilog (TB structures - Class, SVA, etc.), UVM, VCS, Incisive, Scripting skills a + (Python, Perl, ...)**
*
* Experience:

Bachelors and 8+ years of related experience or Masters degree and 6+ years of related experience or PhD and 3+ years of related experience
*** Additional

Job Description:

**** Compensation and Benefits
** The annual base salary range for this position is $108,000 - $172,800.This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.

Broadcom offers a competitive and comprehensive benefits package:
Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
** Broadcom is proud to be an equal opportunity employer.  We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law.  We will also consider qualified applicants with arrest and conviction records consistent with local law.
**** If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.*
* #J-18808-Ljbffr
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